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Features
* High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture
- 120 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation Non-volatile Program and Data Memories - 1K Byte of In-System Programmable Program Memory Flash Endurance: 10,000 Write/Erase Cycles - 64 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - 64 Bytes Internal SRAM - Programming Lock for Self-Programming Flash Program and EEPROM Data Security Peripheral Features - One 8-bit Timer/Counter with Prescaler and Two PWM Channels - 4-channel, 10-bit ADC with Internal Voltage Reference - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator Special Microcontroller Features - debugWIRE On-chip Debug System - In-System Programmable via SPI Port - External and Internal Interrupt Sources - Low Power Idle, ADC Noise Reduction, and Power-down Modes - Enhanced Power-on Reset Circuit - Programmable Brown-out Detection Circuit - Internal Calibrated Oscillator I/O and Packages - 8-pin PDIP/SOIC: Six Programmable I/O Lines Operating Voltage: - 1.8 - 5.5V for ATTINY13V - 2.7 - 5.5V for ATTINY13 Speed Grade - ATTINY13V: 0 - 6 MHz @ 1.8 - 5.5V, 0 - 12 MHz @ 2.7 - 5.5V - ATTINY13: 0 - 12 MHz @ 2.7 - 5.5V, 0 - 24 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption - Active Mode: 1 MHz, 1.8V: 240A - Power-down Mode: < 0.1A at 1.8V
*
*
*
8-bit Microcontroller with 1K Bytes In-System Programmable Flash ATTINY13 Preliminary Summary
* * * * *
Pin Configurations
Figure 1. Pinout ATTINY13
PDIP/SOIC
(PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 GND 1 2 3 4 8 7 6 5 VCC PB2 (SCK/ADC1/T0/PCINT2) PB1 (MISO/AIN1/OC0B/INT0/PCINT1) PB0 (MOSI/AIN0/OC0A/PCINT0)
Rev. 2535CS-AVR-02/04
Note: This is a summary document. A complete document is available on our Web site at www.atmel.com.
Overview
The ATTINY13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATTINY13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2. Block Diagram
Block Diagram
8-BIT DATABUS
STACK POINTER
WATCHDOG OSCILLATOR
CALIBRATED INTERNAL OSCILLATOR
SRAM VCC
WATCHDOG TIMER MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTER0
TIMING AND CONTROL
PROGRAM COUNTER GND PROGRAM FLASH
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
INTERRUPT UNIT PROGRAMMING LOGIC
INSTRUCTION DECODER
X Y Z
CONTROL LINES
ALU
DATA EEPROM
STATUS REGISTER
ADC / ANALOG COMPARATOR
DATA REGISTER PORT B
DATA DIR. REG.PORT B
PORT B DRIVERS
RESET CLKI
PB0-PB5
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ATTINY13
2535CS-AVR-02/04
ATTINY13
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATTINY13 provides the following features: 1K byte of In-System Programmable Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATTINY13 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
Pin Descriptions
VCC GND Port B (PB5..PB0) Digital supply voltage. Ground. Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATTINY13 as listed on page 49. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 12 on page 30. Shorter pulses are not guaranteed to generate a reset.
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2535CS-AVR-02/04
Register Summary
Address
0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x38 0x37 0x36 0x35 0x34 0x33 0x32 0x31 0x30 0x2F 0x2E 0x2D 0x2C 0x2B 0x2A 0x29 0x28 0x27 0x26 0x25 0x24 0x23 0x22 0x21 0x20 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
Name
SREG Reserved SPL Reserved GIMSK GIFR TIMSK0 TIFR0 SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL Reserved TCCR0A DWDR Reserved Reserved Reserved Reserved OCR0B GTCCR Reserved CLKPR Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEARL EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB PCMSK DIDR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Reserved Reserved Reserved
Bit 7
I -
Bit 6
T -
Bit 5
H -
Bit 4
S - SP[7:0] -
Bit 3
V -
Bit 2
N -
Bit 1
Z -
Bit 0
C -
Page
page 6 page 8
- - - - - - - FOC0A
INT0 INTF0 - - - PUD - FOC0B
PCIE PCIF - - - SE - -
- - - - CTPB SM1 - -
- - OCIE0B OCF0B RFLB SM0 WDRF WGM02
- - OCIE0A OCF0A PGWRT - BORF CS02
- - TOIE0 TOV0 PGERS ISC01 EXTRF CS01
- - - -
SELFPRGEN
page 53 page 53 page 70 page 71 page 97 page 70 page 49 page 33 page 66 page 70 page 22
Timer/Counter - Output Compare Register A ISC00 PORF CS00
Timer/Counter (8-bit) Oscillator Calibration Register - COM0A1 COM0A0 COM0B1 COM0B0 DWDR[7:0] - - - - Timer/Counter - Output Compare Register B TSM CLKPCE - - - - - - - - - - - WDTIF WDTIE WDP3 WDCE - - - - - - EEPM1 EEPM0 - - - - - - - - - - - - - PORTB5 DDB5 PINB5 PCINT5 ADC0D PORTB4 DDB4 PINB4 PCINT4 ADC2D - - - - - - - - - - - ACD - ADEN ACBG REFS0 ADSC ACO ADLAR ADATE ACI - ADIF ACIE - ADIE - - ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 PORTB3 DDB3 PINB3 PCINT3 ADC3D PORTB2 DDB2 PINB2 PCINT2 ADC1D PORTB1 DDB1 PINB1 PCINT1 EIN1D PORTB0 DDB0 PINB0 PCINT0 AIN0D EEPROM Address Register EEPROM Data Register EERIE EEMWE EEWE EERE WDE WDP2 WDP1 WDP0 CLKPS3 CLKPS2 CLKPS1 CLKPS0 - - - PSR10 - - WGM01 WGM00
page 69 page 94
page 70 page 73 page 24
page 37
page 14 page 14 page 15
page 51 page 51 page 51 page 54 page 76, page 91
page 74 page 88 page 89 page 90 page 90
ADC Data Register High Byte ADC Data Register Low Byte - ACME - - - - - - ADTS2 ADTS1 ADTS0
page 91
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ATTINY13
2535CS-AVR-02/04
ATTINY13
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
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2535CS-AVR-02/04
Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers
Description
Rd Rd + Rr
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1
ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7)
BRANCH INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
6
ATTINY13
2535CS-AVR-02/04
ATTINY13
Mnemonics
ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (z) R1:R0 Rd P P Rr STACK Rr Rd STACK None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 2 2 1 1 1 N/A 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3
Operands
Rd Rd Rd s s Rr, b Rd, b Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear
Description
Rotate Right Through Carry
Operation
Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0
Flags
Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H
#Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
MCU CONTROL INSTRUCTIONS
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2535CS-AVR-02/04
Ordering Information
Power Supply Speed (MHz) Ordering Code ATTINY13V-12PI ATTINY13V-12PJ(2) ATTINY13V-12SI ATTINY13V-12SJ(2) ATTINY13V-12SSI ATTINY13V-12SSJ(2) ATTINY13-24PI ATTINY13-24PJ(2) ATTINY13-24SI ATTINY13-24SJ(2) ATTINY13-24SSI ATTINY13-24SSJ(2) Package(1) 8P3 8P3 8S2 8S2 S8S1 S8S1 8P3 8P3 8S2 8S2 S8S1 S8S1 Operation Range
12(3)
1.8 - 5.5
Industrial (-40C to 85C)
24(3)
2.7 - 5.5
Industrial (-40C to 85C)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative. 3. For Speed vs. VCC, see "Maximum Speed vs. VCC" on page 116.
Package Type 8P3 8S2 S8S1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)
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ATTINY13
2535CS-AVR-02/04
ATTINY13
Packaging Information
8P3
1
E E1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
9
2535CS-AVR-02/04
8S2
C
1
E
E1
N
L
Top View
End View
e A
SYMBOL
b
COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE
A1
A A1 b C
1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 0 1.27 BSC
2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85 8 4 2, 3 5 5
D
D E1 E L
Side View
e
Notes: 1. 2. 3. 4. 5.
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.
10/7/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO.
R
8S2
REV. C
10
ATTINY13
2535CS-AVR-02/04
ATTINY13
S8S1
1
E1
E
N
Top View
e
b A A1
SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE
D
E E1
5.79 3.81 1.35 0.1 4.80 0.17 0.31 0.4 1.27 BSC 0o
6.20 3.99 1.75 0.25 4.98 0.25 0.51 1.27 8o
Side View
C
A A1 D C
L
b L
End View
e
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc.
7/28/03 TITLE S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. REV. A
R
2325 Orchard Parkway San Jose, CA 95131
S8S1
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2535CS-AVR-02/04
Errata
ATTINY13 Rev. B
The revision letter in this section refers to the revision of the ATTINY13 device. * * * * *
Wrong values read after Erase Only operation High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail Device may lock for further programming debugWIRE communication not blocked by lock-bits Watchdog Timer Interrupt disabled
1. Wrong values read after Erase Only operation At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00). Problem Fix/Workaround If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. Thus no special considerations are needed as long as the erased location is not read before it is programmed. 2. High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail Writing to any of these locations and bits may in some occasions fail. Problem Fix/Workaround After a writing has been initiated, always observe the RDY/BSY signal. If the writing should fail, rewrite until the RDY/BSY verifies a correct writing. This will be fixed in revision D. 3. Device may lock for further programming Special combinations of fuse bits will lock the device for further programming effectively turning it into an OTP device. The following combinations of settings/fuse bits will cause this effect: - 128 kHz internal oscillator (CKSEL[1..0] = 11), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. 9.6 MHz internal oscillator (CKSEL[1..0] = 10), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. 4.8 MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0.
-
-
Problem fix/ Workaround Avoid the above fuse combinations. Selecting longer start-up time will eliminate the problem. 4. debugWIRE communication not blocked by lock-bits When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of program memory and EEPROM data memory can be read even if the lock-bits are set to block further reading of the device. Problem fix/ Workaround Do not ship products with on-chip debug of the tiny13 enabled.
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2535CS-AVR-02/04
ATTINY13
5. Watchdog Timer Interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in interrupt only mode. If the Watchdog is configured to reset the device in the watchdog time-out following an interrupt, the device works correctly. Problem fix / Workaround Make sure there is enough time to always service the first timeout event before a new watchdog timeout occurs. This is done by selecting a long enough time-out period.
ATTINY13 Rev. A
Revision A has not been sampled.
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2535CS-AVR-02/04
Datasheet Change Log for ATTINY13
Changes from Rev. 2535B-01/04 to Rev. 2535C-02/04
Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision.
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
C-code examples updated to use legal IAR syntax. Replaced occurences of WDIF with WDTIF and WDIE with WDTIE. Updated "Stack Pointer" on page 8. Updated "Calibrated Internal RC Oscillator" on page 22. Updated "Oscillator Calibration Register - OSCCAL" on page 22. Updated typo in introduction on "Watchdog Timer" on page 35. Updated "ADC Conversion Time" on page 82. Updated "Serial Downloading" on page 103. Updated "Electrical Characteristics" on page 115. Updated "Ordering Information" on page 8. Removed rev. C from "Errata" on page 12.
Changes from Rev. 2535A-06/03 to Rev. 2535B-01/04
1. 2. 3. 4. 5. 6.
7. 8. 9. 10. 11. 12. 13. 14.
Updated Figure 2 on page 2. Updated Table 12 on page 30, Table 17 on page 39, Table 37 on page 89 and Table 57 on page 116. Updated "Calibrated Internal RC Oscillator" on page 22. Updated the whole "Watchdog Timer" on page 35. Updated Figure 53 on page 103 and Figure 56 on page 108. Updated registers "MCU Control Register - MCUCR" on page 49, "Timer/Counter Control Register B - TCCR0B" on page 69 and "Digital Input Disable Register 0 - DIDR0" on page 76. Updated Absolute Maximum Ratings and DC Characteristics in "Electrical Characteristics" on page 115. Added "Maximum Speed vs. VCC" on page 116 Updated "ADC Characteristics - Preliminary Data" on page 118. Updated "ATTINY13 Typical Characteristics" on page 119. Updated "Ordering Information" on page 8. Updated "Packaging Information" on page 9. Updated "Errata" on page 12. Changed instances of EEAR to EEARL.
14
ATTINY13
2535CS-AVR-02/04
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2535CS-AVR-02/04

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